Fig. 14 illustrates a summary of the power consumption of the battery management chip. The battery management chip consumes 0.838 μA of quiescent current, and its power down current is less than 10 nA. The two current detection circuits and bandgap circuits consume almost more than half of the power.
The state of the battery management chip determines the level of the output terminals, CO and DO, controlling the power switches. Both switches are turned on in the normal state. When the battery is in an overcharge or overcurrent state during charging, switch NM2 must be turned off to prevent the charging of the battery.
The proposed battery management chip had smaller charging current and quiescent current than the charging ICs. In Ref. [ 23 ], it integrated two NMOS and used the integrated NMOS as the current sampling resistor. Therefore, the values of charging and discharging overcurrent will change with the battery voltage.
As the power consumption of wearables significantly decreases [ 19, 20 ], the chip module developed in this paper achieves ultra-low power consumption based on this concept. Fig. 14 illustrates a summary of the power consumption of the battery management chip.
Diagram of a traditional battery management chip. The battery management chip basically has six states: normal, overcharge, undervoltage, charge overcurrent, discharge overcurrent, and power down states. The state of the battery management chip determines the level of the output terminals, CO and DO, controlling the power switches.
The chip mainly includes a bandgap reference, overvoltage detection (OVD) and undervoltage detection (UVD) circuits, discharging and charging overcurrent detection (COCD) circuits, an oscillator, and a timing circuit. Fig. 2. Diagram of a traditional battery management chip.
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