In addition to the external visual characteristics, quality standards for internal microstructure of the chip capacitor are also applicable, as viewed on polished cross sections of capacitor samples. Units are sectioned along the long and short dimension of the capacitor to provide two edge views of the internal electrodes and terminals.
In application, the AC voltage across the chip capacitor may in some cases well exceed the 1.0 ± .02 Vrms test voltage, generating a substantial increase in capacitance.
Chip capacitors destined for high reliability testing are often designed with an added margin of safety, namely maximization of the dielectric thickness, and tested extensively for electrical properties prior to burn-in (e.g., capacitance, dissipation factor, and insulation resistance).
One of the most important parameters in evaluating a high frequency chip capacitor is the Q factor, or the related Equivalent Series Resistance (ESR). In theory, a “perfect” capacitor would exhibit an ESR of 0 (zero) ohms and would be purely reactive with no real (resistive) component.
After describing high reliability testing in our previous article, let’s discuss visual standards for chip capacitors. Multilayer ceramic capacitors (MLCCs) must possess fine workmanship and physical integrity, so visual inspection of the product is performed at 20X magnification to check for defects in the capacitor body and end metallization.
The quality factor Q, is a dimensionless number that is equal to the capacitor’s reactance divided by the capacitor’s parasitic resistance (ESR). The value of Q changes greatly with frequency as both reactance and resistance change with frequency.
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